1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having an SOI-MOS transistor which prevents a substrate floating effect.
2. Description of the Background Art
An MOS transistor provided in a semiconductor layer formed on an insulating layer is generally called an SOI-MOS (Silicon On Insulator-Metal Oxide Semiconductor) transistor. Since the SOI-MOS transistor isolates elements by insulation, and can isolate the elements including a substrate completely, it suffers from a less leakage current, and has a higher current driving ability. Further, the SOI-MOS transistor can suppress a short channel effect and the like.
Therefore, the SOI-MOS transistor is expected as a future basic structure of a transistor used in a memory device and a logic circuit on the order of quarter micron. A typical structure of the SOI-MOS transistor is shown in FIG. 30. The SOI-MOS transistor includes a pair of n.sup.+ type source/drain regions 3 positioned on both sides of a gate wiring 17 formed on an active region 5. The n.sup.+ type source/drain region 3 is connected with another element (not shown) through an n.sup.+ type source/drain contact 9. A transistor having such a structure as described above raises various problems as miniaturization progresses. More specifically, when the channel length becomes shorter than 1 .mu.m, there occur a steep current rising in the I.sub.D -I.sub.G characteristics, a kink phenomenon in the I.sub.D --V.sub.D characteristics, decrease of the source/drain breakdown voltage, a latch phenomenon in the I.sub.D -V.sub.G characteristics and the like, as described in Handotai Kenkyu 40, published by Kogyochosakai: 166 and 167.
These phenomena cause characteristics of the SOI-MOS transistor to degrade. Such degradation of the characteristics is due to a substrate floating effect. The substrate floating effect is called a parasitic bipolar effect.
The parasitic bipolar effect will be described with reference to FIG. 31. When a drain voltage is increased, an electric field in a channel direction becomes substantially large in the vicinity of a drain region 33. An electron 30 in an effective channel region 11 positioned underneath gate wiring 17 is accelerated (indicated by a reference number 31) by this strong electric field to attain a high energy state. The electron in this state collides (indicated by a reference number 34) with a silicon atom in the vicinity of an end portion of drain region 33 to generate a large number of electron-hole pairs. An electron 35 of the electron-hole pair generated by impact ionization is attracted by a high drain electric field to flow in drain region 33 to form part of a drain current. On the other hand, a hole 7 is carried back by the drain electric field to be stored underneath effective channel region 11.
When the holes generated by impact ionization are stored under effective channel region 11 as described above, the potential in the vicinity of effective channel region 11 and a source region 32 increases, causing the height of a source-drain potential barrier to decrease and inducing injection of an electron 36 from source region 32. This causes the above described parasitic bipolar effect.
As a direct method for preventing such a parasitic bipolar effect caused by the substrate floating effect, a channel potential fixation structure for fixing the potential in a channel region has been proposed. For example, an H-shaped channel potential fixation structure having H-gate wiring 17 as shown in FIG. 32 and a T-shaped channel potential fixation structure having T-gate wiring 17 as shown in FIG. 33 or 34 are disclosed by J. Colinge, "Silicon-on-Insulator Technology" :102-104, for example.
Referring to FIG. 32, active region 5 is divided into four regions by H-gate wiring 17 having a first wiring 1, a second wiring 2, and a third wiring 14. More specifically, the pair of n.sup.+ type source/drain regions 3 having n.sup.+ type source/drain contacts 9 are positioned on both sides of first wiring 1 sandwiched by one side portion of second wiring 2 and one side portion of third wiring 14 opposite thereto. A p.sup.+ type channel potential fixing region 4 is positioned on the respective other side portions of second wiring 2 and third wiring 14. A region underneath gate wiring 17 is of p type. Effective channel region 11 is under first wiring 1.
Referring to FIG. 33 or 34, active region 5 is divided into three regions by T-gate wiring 17 having first wiring 1 and second wiring 2. The pair of n.sup.+ type source/drain regions 3 are positioned on both side portions of first wiring 1 on one side portion of second wiring 2. On the other side portion of second wiring 2, p.sup.+ type channel potential fixing region 4 is positioned. Underneath first wiring 1 is p type effective channel region 11.
In the above described SOI-MOS transistor structure, holes flowing in effective channel region 11 pass through the p type region positioned under second wiring 2 or third wiring 14 to p.sup.+ type channel potential fixing region 4 to be ejected by a p.sup.+ type channel potential fixing contact 10. As a result, the substrate floating effect can be prevented.
Then, consider a transistor formed by connecting a plurality of SOI-MOS transistors each having such a structure. FIG. 35 shows a transistor in which two SOI-MOS transistors shown in FIG. 32 are connected laterally in series. As shown in FIG. 35, second wirings 2 and third wirings 14 of the two transistors are connected to each other. Therefore, the gate potentials of the two transistors are the same. Since the potentials of individual transistors cannot be controlled, this transistor structure cannot be used in general. Further, in such an SOI-MOS transistor as shown in FIG. 36, second wirings 2 of individual transistors are connected to each other, so that the gate potentials of the transistors are the same. Therefore, the SOI-MOS transistor shown in FIG. 36 cannot be used in general.
In the structure shown in FIG. 32, 33, 35, or 36, second wiring 2 or third wiring 14 is formed on the active region excluding effective channel region 11. These wirings serve as a mask material in formation of p.sup.+ type channel potential fixing region 4. However, these wirings increase the capacity of the gate wiring and underlying active region 5, causing the processing speed of the transistor to decease.
When two SOI-MOS transistors shown in FIG. 34 are connected in series, such a structure as shown in FIG. 37 can be formed. In this structure, the gate wirings of respective transistors are not connected to each other, and the channel potentials can be fixed individually.
However, the SOI-MOS transistor shown in FIG. 34 has a problem in its manufacturing process. More specifically, if mask deviation occurs in formation of the gate wiring, one end portion of second wiring 2 may be formed within active region 5 as shown in FIG. 38 (indicated by B in the figure). First wiring 1 and second wiring 2 serve as a mask for ion implantation in forming p.sup.+ type channel potential fixing region 4 for channel potential fixation. Therefore, if the gate wiring is formed as shown in FIG. 38, p.sup.+ type ions are to be implanted also in part of n.sup.+ type source/drain region 3. As a result, the breakdown voltage between n.sup.+ type source/drain region 3 and p.sup.+ type channel potential fixing region 4 cannot be maintained, and this SOI-MOS transistor cannot serve as a transistor. Note that in FIG. 38, the corners of the pattern are curved by diffraction at the time of exposure.
Further, the area of n.sup.+ type source/drain contact 9 formed in n.sup.+ type source/drain region 3 decreases with miniaturization of the device. The reduced contact area increases the resistance of the contact, and deteriorates the electric characteristics of the transistor.
As described above, in order to prevent the parasitic bipolar effect caused by the substrate floating effect in the conventional SOI-MOS transistor, such a structure as including the channel potential fixing region as shown in FIGS. 32 to 34 has been considered. However, when a plurality of SOI-MOS transistors are connected, gate wirings of the respective transistors are connected to each other. Therefore, the gate potentials of the individual transistors cannot be controlled, and this structure cannot be used in general.
Even if such a structure as shown in FIG. 37 is employed which can control the gate potentials of the individual transistors, there is a problem associated with mask deviation in forming the gate wiring. More specifically, as shown in FIG. 38, n.sup.+ type source/drain region 3 and p.sup.+ type channel potential fixing region 4 are electrically connected. Therefore, this structure does not function as a transistor.
Further, it is necessary to form second wiring 2 or third wiring 14 as shown in FIG. 32 or 33 in order to add p.sup.+ type channel potential fixing region 4. This increases a so-called gate capacity of the gate wiring and the active region, causing the processing speed to decrease.
With miniaturization of the device, the size of n.sup.+ type source/drain contact 9 connected to n.sup.+ type source/drain region 3 becomes smaller in FIG. 32 or 33. This decreases the contact area, thereby increasing the contact resistance to deteriorate the electric characteristics.